(1) FIELD OF THE INVENTION
The present invention relates to the fabrication of semiconductor devices, and more specifically to a process for fabricating complimentary metal oxide semiconductor, (CMOS), devices.
(2) DESCRIPTION OF PRIOR ART
The semiconductor industry is continually striving to improve the performance of silicon devices, while still maintaining or even reducing the cost of manufacturing higher performing silicon chips. These objectives have been realized, in part, by micro-miniaturazation, or the ability of the semiconductor industry to reduce the dimensions of key features of the silicon device. The ability of the semiconductor industry to produce sub-micron features has allowed smaller silicon chips to result, thus allowing more chips per starting substrate, ultimately reducing the cost of individual chips. The reduction in the dimensions of key silicon device features has also resulted in performance benefits, realized via reductions in performance degrading capacitances and resistances. Micro-miniaturazation has been accomplished by the advances in several semiconductor fabrication disciplines, such as photolithography and dry etching. The development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have resulted in the attainment of sub-micron images in photoresist. Similar advancements in the dry etching discipline has allowed the sub-micron images in photoresist to be successfully transferred to underlying materials, used for the fabrication of advanced semiconductor devices.
However, the objective of cost reduction can only be partially achieved via micro-miniaturazation. Significant cost reductions can also be realized by reducing the complexity and cycle time used to fabricate semiconductor devices. Reductions in the number of photomasking steps used to produce the desired device can result in the desired device cost reduction. For example Gilgen, et al, in U.S. Pat. No. 5,134,085, describe a dynamic random access memory, (DRAM), process in which significant reductions in photomasking have been applied, resulting in a DRAM device, fabricated at a lower cost then counterparts using a greater number of photomasking process steps. This invention will describe a CMOS process in which only six photomasking steps are used to produce CMOS devices, through first metal processing. This is accomplished by the use of a high energy ion implantation twin-tub process, a single mask lightly doped, and heavily doped, N type source and drain region, and a self-aligned P+ source and drain formation technique.